November 15, 2011

GOEPEL electronic and TELEFUNKEN Semiconductors accelerate deployment of system-level JTAG applications

Jena; Munich – today during the 2011 Productronica trade fair GÖPEL electronic, the worldwide leading supplier of JTAG/boundary scan solutions based on IEEE1149.x announced support for the TELEFUNKEN Semiconductors TF112 JTAG scan-path multiplexer. The TF112 is a new 7 port multidrop multiplexer that facilitates multiple scan chains for complex cards and system level boundary scan. Göpel’s proprietary boundary scan software tool SYSTEM CASCON includes a unique scan-router-functional library that provides automated addressing and routing of multiple scan paths even in hierarchical configurations. The new tool provides fully automated boundary scan testing, in-system programming and emulation for both board and system level.

“By developing this new function library for automated control of the TF112 we are not only supporting these powerful IEEE1149.1 multiplexers from TELEFUNKEN Semiconductors but stimulating the use of hierarchical multi-drop architectures for improved test and programming of complex boards and systems” said Thomas Wenzel, General Manager of the Boundary Scan Division of GÖPEL electronic. “The combination of our proprietary software tools together with the scan-multiplexer products from TELEFUNKEN Semiconductors provides the user with enhanced and innovative capabilities within a known and proven framework”.

“We are extremely pleased to be working with GÖPEL, the market leader for professional JTAG/Boundary Scan solutions as a partner on present and future innovative solutions”, pointed out Herbert Scheitler, Director of European Sales for TELEFUNKEN Semiconductors. Added Marketing Director Ken Filliter, “After the initial step with the TF112 we expect to provide users with continued improvements using these aligned software and hardware tools”.

The TF112 functional library supports the entire development sequence, beginning with the automatic recognition of the scan-path coming from CAD-data, the automatic-test-pattern-generation (ATPG), followed by pin-error level diagnostics (PFD), graphical failure localization and debugging, as well as in-system programming (ISP) of FLASH/PLD/MCU all in an integrated environment. Boundary scan operations involving multiple TF112s will be totally transparent and synchronized. This fully automated flow eliminates the need for manual jumpers improving efficiency time and reducing the chance of error.

The SYSTEM CASCON tool handles secondary scan paths in a dynamic manner, and one, multiple, or all of the associated TAPS may be active at one time. The tool makes use of the PARK and UNPARK instructions to control various TAPS as needed. There is no need for manual designation of scan paths and instead the ATPG tools both generate the test vectors and control the TF112s for board level interconnect and card-to-card testing over backplanes or cables. CPLD programming on secondary scan chains is likewise automated including programming via IEEE1532, SFV, or JAM/STAPL. JTAG/IEEE1149.1 testing as well as AC-JTAG, IEEE1149.6 for AC-coupled nets is available.

The new software library functions for the TF112 are SYSTEM CASCON version 4.6 integrated as a standard and will be activated via license manager. The release is available now and free of charge for users with existing software licenses.