INTERFACE PRODUCTS

The TF90LVDS031 is a 400 Mbps Quad LVDS (low voltage differential signaling) Line Driver optimized for high-speed, low power, low noise transmission over controlled impedance (approximately 100 Ω) transmission media (e.g. cables, printed circuit board traces, backplanes).

The TF90LVDS032 and TF90LVDT032 are 400 Mbps Quad LVDS (low voltage differential signaling) Line Receivers optimized for high-speed, low power, low noise transmission over controlled impedance (approximately 100 Ω) transmission media (e.g. cables, printed circuit board traces, backplanes).
The TF90LVDS032 and TF90LVDT032 accept four LVDS signals and translates them to four LVCMOS signals. Their outputs can be disabled and put in a high-impedance state via two enable pins, OE and OE*.
The TF90LVDS032 and TF90LVDT032 input receivers support wide input voltage range. A fail-safe feature sets the outputs to a high state when the inputs are shorted, open, or undriven.

The TF90LVDS032 and TF90LVDT032 are 400 Mbps Quad LVDS (low voltage differential signaling) Line Receivers optimized for high-speed, low power, low noise transmission over controlled impedance (approximately 100 Ω) transmission media (e.g. cables, printed circuit board traces, backplanes).
The TF90LVDS032 and TF90LVDT032 accept four LVDS signals and translates them to four LVCMOS signals. Their outputs can be disabled and put in a high-impedance state via two enable pins, OE and OE*.
The TF90LVDS032 and TF90LVDT032 input receivers support wide input voltage range. A fail-safe feature sets the outputs to a high state when the inputs are shorted, open, or undriven.

The TF90LVDS047 is a 400 Mbps Quad LVDS (low voltage differential signaling) Line Driver optimized for high-speed, low power, low noise transmission over controlled impedance (approximately 100 Ω) transmission media (e.g. cables, printed circuit board traces, backplanes).
The TF90LVDS047 accepts four LVCMOS / LVTTL signals and translates them to four LVDS signals. Its differential outputs can be disabled and put in a high-impedance state via two enable pins, OE and OE*. Its flow-through pinout simplifies PCB layout and minimizes crosstalk by isolating the LVDS outputs from the LVCMOS / LVTTL inputs
Low 350 ps (max) channel-channel skew and 250 ps (max) pulse skew ensure reliable communication in high-speed links that are highly sensitive to timing error.

The TF90LVDS048 and TF90LVDT048 are 400 Mbps Quad LVDS (low voltage differential signaling) Line Receivers optimized for high-speed, low power, low noise transmission over controlled impedance (approximately 100 Ω) transmission media (e.g. cables, printed circuit board traces, backplanes).
The TF90LVDS048 and TF90LVDT048 input receivers support wide input voltage range of -7V to 12V for exceptional noise immunity.
The TF90LVDS048 and TF90LVDT048 accept four LVDS signals and translate them to four LVCMOS signals. The outputs can be disabled and put in a high-impedance state via two enable pins, OE and OE*. The flow-through pinout simplifies PCB layout and minimizes crosstalk by isolating the LVDS inputs from the LVCMOS / LVTTL outputs.
The TF90LVDT048 features on-chip 100 Ω input termination resistors that minimize input return loss, component count and board space. The TF90LVDS048 differential inputs are without input termination resistors and are suitable for applications requiring custom termination schemes.

The TF90LVDS048 and TF90LVDT048 are 400 Mbps Quad LVDS (low voltage differential signaling) Line Receivers optimized for high-speed, low power, low noise transmission over controlled impedance (approximately 100 Ω) transmission media (e.g. cables, printed circuit board traces, backplanes).
The TF90LVDS048 and TF90LVDT048 input receivers support wide input voltage range of -7V to 12V for exceptional noise immunity.
The TF90LVDS048 and TF90LVDT048 accept four LVDS signals and translate them to four LVCMOS signals. The outputs can be disabled and put in a high-impedance state via two enable pins, OE and OE*. The flow-through pinout simplifies PCB layout and minimizes crosstalk by isolating the LVDS inputs from the LVCMOS / LVTTL outputs.
The TF90LVDT048 features on-chip 100 Ω input termination resistors that minimize input return loss, component count and board space. The TF90LVDS048 differential inputs are without input termination resistors and are suitable for applications requiring custom termination schemes.

The TF10CP02 and TF10CP22 are low-jitter, fully differential, non-blocking LVDS 2x2 crosspoint switches ideal for applications that require high-speed data or clock distribution, switching, buffering, muxing or routing while minimizing power, space, and noise.

The TF10CP02 and TF10CP22 are low-jitter, fully differential, non-blocking LVDS 2x2 crosspoint switches ideal for applications that require high-speed data or clock distribution, switching, buffering, muxing or routing while minimizing power, space, and noise.

The Single Channel M-LVDS transceiver family consist of 6 devices that have two types of M-LVDS inputs and three drive strengths of M-LVDS and LVCMOS outputs. The two inputs meet the TIA/EIA-899 standard for type 1 (data) and type 2 (control) inputs. New to the M-LVDS family of devices are the variable edge rates that are optimized for three frequency ranges.
These Transceivers are half-duplex with bidirectional bus pins that are TIA/EIA-899 compliant and LVCMOS level signals. The device consist of a receiver and a driver. The receiver converts the M-LVDS bus signals to an LVCMOS output whereas the driver converts the LVCMOS inputs to M-LVDS bus signals.

The Single Channel M-LVDS transceiver family consist of 6 devices that have two types of M-LVDS inputs and three drive strengths of M-LVDS and LVCMOS outputs. The two inputs meet the TIA/EIA-899 standard for type 1 (data) and type 2 (control) inputs. New to the M-LVDS family of devices are the variable edge rates that are optimized for three frequency ranges.
These Transceivers are half-duplex with bidirectional bus pins that are TIA/EIA-899 compliant and LVCMOS level signals. The device consist of a receiver and a driver. The receiver converts the M-LVDS bus signals to an LVCMOS output whereas the driver converts the LVCMOS inputs to M-LVDS bus signals.

The Single Channel M-LVDS transceiver family consist of 6 devices that have two types of M-LVDS inputs and three drive strengths of M-LVDS and LVCMOS outputs. The two inputs meet the TIA/EIA-899 standard for type 1 (data) and type 2 (control) inputs. New to the M-LVDS family of devices are the variable edge rates that are optimized for three frequency ranges.
These Transceivers are half-duplex with bidirectional bus pins that are TIA/EIA-899 compliant and LVCMOS level signals. The device consist of a receiver and a driver. The receiver converts the M-LVDS bus signals to an LVCMOS output whereas the driver converts the LVCMOS inputs to M-LVDS bus signals.

The TF112 combines a 7 port IEEE1149.1 (JTAG) multiplexer with addressable multidrop capability. As a multiplexer, 7 local ports allow partitioning of scan chains to simplify and accelerate programming and test and debug sequences. Op- tional daughter cards or ICs are easily handled with dedicated scan chains. Local chains can be selected individually or in combination as required.

Addressable multi-drop capability allows operation on a backplane with other TF112s or similar addressable devices. 8 address pins are used to set the unique device address. Ad- dressing the device is accomplished by loading the instruc- tion register with a value matching the address pins.

The backplane port and one of the local ports are bi-directional and may be set as master or slave. This feature enables multi- master operation.

All major ATPG vendors support this function and both ad- dressing and selection of local ports is handled automatically by the vector generation software.